1. Field of the Invention
The present invention relates to a display apparatus, and more particularly, to a plasma display apparatus.
2. Background of the Related Art
In general, a plasma display apparatus has a plasma display panel and a driver for driving the plasma display panel.
The plasma display panel has a front panel and a rear panel. A barrier rib formed between the front panel and the rear panel forms one unit cell. Each cell is filled with an inert gas containing a primary discharge gas, such as neon (Ne), helium (He) or a mixed gas of Ne+He, and a small amount of xenon (Xe). If the inert gas is discharged with a high frequency voltage, it generates vacuum ultraviolet rays. The vacuum ultraviolet rays excite phosphors formed between the barrier ribs, thereby implementing images.
FIG. 1 is a perspective view illustrating the construction of a general plasma display panel.
As shown in FIG. 1, the plasma display panel has a front panel 100 and a rear panel 110. In the front panel 100, a plurality of sustain electrode pairs in which scan electrodes 102 and sustain electrodes 103 are formed in pairs is arranged on a front glass 101 serving as a display surface on which images are displayed. In the rear panel 110, a plurality of address electrodes 113 crossing the plurality of sustain electrode pairs is arranged on a rear glass 111 serving as a rear surface. At this time, the front panel 100 and the rear panel 110 are parallel to each other with a predetermined distance therebetween.
The front panel 100 has the pairs of the scan electrodes 102 and the sustain electrodes 103, which mutually discharge the other and maintain the emission of a cell within one discharge cell. In other words, each of the scan electrode 102 and the sustain electrode 103 has a transparent electrode “a” formed of a transparent ITO material and a bus electrode “b” formed of a metal material. The scan electrodes 102 and the sustain electrodes 103 are covered with one or more dielectric layers 104 for limiting a discharge current and providing insulation among the electrode pairs. A protection layer 105 having Magnesium Oxide (MgO) deposited thereon is formed on the dielectric layers 104 so as to facilitate discharge conditions.
In the rear panel 110, barrier ribs 112 of stripe form (or well form), for forming a plurality of discharge spaces, i.e., discharge cells are arranged parallel to one another. Furthermore, a plurality of address electrodes 113, which generate vacuum ultraviolet rays by performing an address discharge, are disposed parallel to the barrier ribs 112. R, G and B phosphor layers 114 that radiate a visible ray for displaying images during an address discharge are coated on a top surface of the rear panel 110. A dielectric layer 115 for protecting the address electrodes 113 is formed between the address electrodes 113 and the phosphor layers 114.
A method of implementing gray levels of an image in the plasma display panel constructed above will be described below with reference to FIG. 2.
FIG. 2 is a view illustrating a method of implementing gray levels of an image of the plasma display panel in the related art.
As shown in FIG. 2, in the method of implementing gray levels of an image in the plasma display panel, one frame is divided into several sub-fields, each having a different number of emissions. Each of the sub-fields is again divided into a reset period (RPD) for initializing the entire cells, an address period (APD) for selecting a discharge cell to be discharged, and a sustain period (SPD) for implementing gray levels depending on a discharge number. For example, if it is sought to display images with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 seconds is divided into eight sub-fields (SF1 to SF8) as shown in FIG. 2. Each of the eight sub-fields (SF1 to SF8) is again divided into a reset period, an address period and a sustain period.
The reset period and the address period of each sub-field are the same every sub-field. Furthermore, an address discharge for selecting a discharge cell to be discharged is generated because of a voltage difference between the data electrodes and the scan electrodes, i.e., transparent electrodes. The sustain period is increased in the ratio of 2n (where n=0, 1, 2, 3, 4, 5, 6, 7) in each sub-field. Since a sustain period is different in each sub-field as described above, gray levels of an image are represented by controlling a sustain period of each sub-field, i.e., a sustain discharge number.
FIG. 3 is a schematic circuit diagram of a scan driving apparatus for driving the related art plasma display panel.
As shown in FIG. 3, the scan driving apparatus of the related art plasma display panel bas an energy recovery circuit 40, a drive IC 52, a set-up supply unit 42, a set-down supply unit 47, a negative scan voltage supply unit 46, a scan reference voltage supply unit 50, a seventh switch Q7 connected between the set-up supply unit 42 and the drive IC 52, and a sixth switch Q6 connected between the set-up supply unit 42 and the energy recovery circuit 40.
The drive IC 52 is electrically connected to scan electrodes in a push/pull form, and applies a pulse of a driving waveform to the scan electrodes.
The energy recovery circuit 40 supplies the scan electrodes with a sustain voltage (Vs) and a sustain pulse (sus).
The negative scan voltage supply unit 46 sequentially supplies a write scan voltage (−Vy) for selecting a cell, which will be turned on, to the scan electrodes via the drive IC 52.
The scan reference voltage supply unit 50 supplies a voltage of a reference voltage source (Vsc) to the scan electrodes via the drive IC 52.
The set-up supply unit 42 receives the sum of the sustain voltage (Vs) output from the energy recovery circuit 40 and a voltage value of a set-up voltage source (Vsetup) and applies a ramp-up pulse (Ramp-up), which rises from the sustain voltage (Vs) with a predetermined gradient, to the scan electrodes via the drive IC 52.
The set-down supply unit 47 applies a ramp-down pulse (Ramp-down), which falls from the sustain voltage (Vs) output from the energy recovery circuit 40 with a predetermined gradient, to the scan electrodes via the drive IC 52.
FIG. 4 shows a driving waveform illustrating a method of driving the scan driving apparatus of the related art plasma display panel shown in FIG. 3.
A driving waveform generated by the scan driving apparatus of FIG. 4 will now be described with reference to FIG. 3. It is first assumed that a second capacitor C2 is charged with a voltage of the set-up voltage source (Vsetup) and the sustain voltage (Vs) is applied from the energy recovery circuit 40 to a first node n1 at a turned-on point of a fifth switch Q5.
During the set-up period (SU), the fifth switch Q5 and the seventh switch Q7 are turned on. At this time, the sustain voltage (Vs) is supplied from the energy recovery circuit 40. The sustain voltage (Vs) supplied from the energy recovery circuit 40 is supplied to scan electrode lines Y1 to Ym via an internal diode of the sixth switch Q6, the seventh switch Q7 and the drive IC 52. Therefore, voltages of the scan electrode lines Y1 to Ym abruptly rise to Vs.
Meanwhile, since the voltage (Vs) is supplied to a negative end of the second capacitor C2, the second capacitor C2 applies a voltage (Vs+Vsetup) to the fifth switch Q5. The fifth switch Q5 supplies a voltage, which is received from the second capacitor C2, to the first node n1 with a predetermined gradient while having its channel width controlled by a first variable resistor VR1 disposed at its front side. The voltage, which is supplied to the first node n1 with a predetermined gradient, is applied to the scan electrode lines Y1 to Ym via the seventh switch Q7 and the drive IC 52. At this time, the scan electrode lines Y1 to Ym are supplied with a ramp-up pulse (Ramp-up).
In this case, an amount of the set-up voltage source (Vsetup) is greater than the sum (Vsc+Vy) of the sustain voltage (Vs), an amount (Vsc) of the scan reference voltage source or an amount (Vy) of the write scan voltage source. Therefore, the highest voltage of the ramp-up pulse (Ramp-up) is twice greater than the sustain voltage (Vs) and luminance of a dark discharge becomes great. As a result, a problem arises because a contrast ratio is lowered.
After the ramp-up pulse (Ramp-up) is supplied to the scan electrode lines Y1 to Ym, the fifth switch Q5 is turned off. If the fifth switch Q5 is turned off, only the voltage (Vs) supplied from the energy recovery circuit 40 is applied to the first node n1. Accordingly, the voltages of the scan electrode lines Y1 to Ym abruptly fall to Vs.
Thereafter, in the set-down period (SD), while the seventh switch Q7 is turned off, a tenth switch Q10 is turned on. The tenth switch Q10 falls the voltage of the second node n2 to the write scan voltage (−Vy) with a predetermined gradient while having its channel width controlled by a second variable resistor VR2 disposed at its front side. At this time, the ramp-down pulse (Ramp-down) is supplied to the scan electrode lines Y1 to Ym.
The set-up supply unit 42 and the set-down supply unit 47 supply the ramp-up pulse (Ramp-up) and the ramp-down pulse (Ramp-down) to the scan electrode lines Y1 to Ym during the reset period, while repeating the above process.
In the related art driving apparatus, however, since a voltage difference between voltages applied to the first node n1 and the second node n2 is great, the seventh switch Q7 having a high withstanding voltage must be used. Therefore, a problem arises because the manufacturing cost is high.
The seventh switch Q7 has an internal diode in a direction different from that of the sixth switch Q6. The internal diode functions to prevent a voltage applied to the second node n2 from being supplied to a ground voltage (GND) via the internal diode of the sixth switch Q6 and the internal diode of the fourth switch Q4. Meanwhile, during the set-down period, the voltage (Vs) is applied to the first node n1, and the write scan voltage (−Vy) is applied to the second node n2. In this case, if the voltage (Vs) is set to approximately 180V and the write scan voltage (−Vy) is set to −70V, the seventh switch Q7 must have a withstanding voltage of about 250V (300V when considering actual driving voltage margin). That is, in the related art, a switching element having a high withstanding voltage must be disposed in the seventh switch Q7. Therefore, a problem arises because the manufacturing cost is high.
Furthermore, the reset voltage and the sustain voltage pass through the sixth switch Q6 and the seventh switch Q7. Therefore, the sixth switch Q6 and the seventh switch Q7 must be a switch that applies a set-up waveform and has a high withstanding voltage higher than the reset voltage. Therefore, there are problems in that the cost is high, heat is generated and energy lost is high.